This invention relates to a memory controller and a memory control method that are applied to a multiprocessor system, and more particularly to a memory controller and a memory control method that synchronize the data stored by a memory bank method.
Multiprocessor systems have been provided with a memory controller that manages and controls the memory-bank-type shared main memory and that executes access instructions (including data and addresses) in an out-of-order manner or a weak-order manner.
The memory controller has not only the function of independently controlling each bank memory corresponding to an independent memory area but also the function of replacing weak-order synchronization with strong-order synchronization temporarily. The methods related to such synchronizing operation are roughly divided as follows.
A first method is such that a buffer memory with a first-in, first-out (FIFO) function is used for address operation and the access instructions issued from the processors are executed in the order in which the address operations have been accepted. In this method, it is assumed that the system has the address bus separated from the data bus. Here, the address operation means the operation of the address bus.
A second method is such that a management table, called a scoreboard, that manages the progress of operation (the operating state of access instructions) in units of an independent control range of memory (bank memory units). With the method, once a synchronizing operation has been executed, the acceptance of an address operation is refused until the preceding operation has been completed. Namely, the synchronizing process is assured by retrying the synchronizing operation.
Because the second method shortens the latency in a read operation (read access operation) executed after a write operation (memory write access operation) and increases the memory use efficiency as compared with the first method, it improves the throughput of the system in actual operation.
These methods, however, have the following problems. The first method assures the execution of a synchronizing operation by using a buffer memory with an FIFO function for address operation. On the system, however, data operations (the operation of the data bus) are not always executed in the order of address operations. Therefore, the incompletion of the data operations causes a state where all of the FIFO buffer for address operation has been used, so that a state where the acceptance of an address operation is refused (retried) is liable to take place. In addition, the first method has an disadvantage in that when the data transfer for the preceding write operation has not been finished, all of the subsequent read operations cannot be executed, resulting in a larger latency in the read operation.
The second method manages the state of operations by the use of a management table, so that it can perform a memory access operation in an out-of-order manner or a weak order manner. But once the operations have been synchronized, the subsequent operations (or the operations satisfying the synchronizing conditions) cannot be executed until the preceding operation has been completed, leading to the problem of increasing the overhead of the system in the synchronizing process.